The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device which, during the formation of an interlevel dielectric layer, removes the defects created between the interface of the interlevel dielectric layer and a conducting layer to enhance reliability.
To improve performance of semiconductor devices, fineness and high packing density are essential. High packing density can be accomplished by reducing the device size itself. For example, devices previously formed on one layer are instead separately constructed on multiple layers in a multilevel metallization structure. In such a multilevel metallization structure, in order to form a second wire-layer pattern on a first wire-layer pattern, an interlevel dielectric layer is thus formed between the wire layers. Planarization becomes a crucial requirement.
To form a conductive layer and an interlevel dielectric layer for metallization, it is known to first form a conductive material layer on a substrate, which is then patterned by a photo-etching step to form the conductive layer. The interlevel dielectric layer is then formed on the conductive layer and a planarization step is carried out. Planarization of the interlevel dielectric layer is generally classified as an inter-metal dielectric (IMD) process and an inter-layer dielectric (ILD) process.
The IMD process is a composite process using, for example, a spin-on-glass (SOG) layer. When a conductive layer is formed of aluminum having a low melting point, as in the SOG composite process, the planarization is performed by in-situ deposition and an etching step. However, since the composite process using the SOG layer employs many steps, the process is known to have a high probability of producing a crack in the SOG layer of the formed device.
The ILD process is a widely used process in which, for instance, BPSG is deposited and thermally treated at a temperature over 850.degree. C. to planarize the interlevel dielectric. R. A. Levy and K. Nassau disclose such a process in Solid State Technol., pp 123-129 (October, 1986), reporting that the viscous behavior of phosphosilicate-glass (PSG) and BPSG in VLSI processing reduces thermal damage to the devices.
However, the ILD process described above, using BPSG becomes difficult, as devices become minute, because low temperature flowing (lowering of the treating temperature of the BPSG) required for such minute device deteriorates the evenness of the interlevel dielectric layer. Thus, forming a low-resistant conductive layer and an interlevel dielectric layer having excellent evenness characteristic is difficult using known processing methods. This is particularly true if tungsten is used in the conductive structure (such as, for a bit line in memory) because the tungsten becomes oxidized in succeeding heat treatment.
Recently, a modified planarization process using the low-temperature flow of BPSG has also been widely employed. To decrease the flow temperature of the BPSG, the flow atmosphere can be modified or the concentration of boron (B) or phosphorus (P) in the BPSG can be increased. Of these, the method using a BPSG layer containing B or P in high concentration is preferred.
However, when the concentration of B is increased over a specific level (about 4 wt %), boric acid crystal is created and causes cracking. Thus, increasing the concentration of B has an upper limit. When the interlevel dielectric layer is formed using BPSG containing P of high-concentration, an excessive amount of P ions move toward the conductive layer in which polycrystalline silicon is present during flowing. This produces bubbles on the interface between the conductive layer and the interlevel dielectric layer. Later heat treatment increases the size of the bubbles. The thicker the P concentration is, the more serious this problem becomes.
Studies on the bubbles formed due to the use of BPSG containing P of high concentration are disclosed by D. S. Williams and E. A. Dein, J. Electrochem. Soc., vol. 134, pp 657-664(1987) and by Hideki Takeuchi and Junichi Muroto, ibid, vol. 131, pp 403-472(1984). The formed bubbles may be opened during a succeeding step of forming a contact opening, to then possibly causing a short between conductive layers and deteriorating the reliability of the semiconductor device.
FIGS. 1A-1C sequentially show a planarization process of a conventional method using BPSG of high concentration.
Referring to FIG. 1A, a first interlevel dielectric layer 2, for instance, a BPSG layer, is formed on a semiconductor substrate 1. A polycrystalline silicon layer 3 doped with an impurity and a conductive material layer 4 (made of Wsi) are formed thereon. The conductive material layer is patterned by a photo-etching step into a predetermined pattern to form a conductive layer 12, for instance, a bit line. When conductive layer 12 is made of polycrystalline silicon or tungsten-silicide having a relatively high melting point, planarization is performed by the deposition and flow of the BPSG layer.
Subsequently, BPSG layer 6, containing a high concentration of P, is formed on the overall surface of conductive layer 12 as a second interlevel dielectric layer and is thermally treated to planarize the resultant structure.
In order to overcome the poor step coverage due to high packing density, as shown in FIG. 1B, another BPSG layer is formed on BPSG layer 6 as a third interlevel dielectric layer 7. The planarization layer is formed with two layers because, when the planarization layer is formed with a single layer, the surface unevenness of the lower structure cannot be controlled to the required degree. Thus, the planarization layer is formed with usually two, and sometimes three, layers to obtain an even planar surface.
Then, as shown in FIG. 1C, a contact opening 8 is formed in a predetermined portion.
When the BPSG of high concentration is deposited on conductive layer 12 and is thermally treated in the conventional method as described above (FIG. 1A), an excessive amount of phosphorus (P) ions in the BPSG produces bubbles 10 between the surfaces of the BPSG layer and conductive layer 12. The bubbles 10 increase in size during the succeeding heat treatment, as shown in FIG. 1B.
If the bubbles are formed, during the forming of the contact opening,.the bubbles can then be opened (as in FIG. 1C) to cause shorts between conductive layers. This decreases the reliability of the device.